Tesla FSD Chip

The Tesla FSD (Full Self-Driving) chip is Tesla's proprietary automotive-grade autonomous driving computing processor, powering its on-board FSD computing platform. Since its in-house silicon first debuted on HW3.0 in 2019, the FSD chip has evolved across several generations through to AI5, with compute performance leaping from an initial 144 TOPS (dual-chip) to between 2,000 and 2,500 TOPS, serving as the core hardware backbone driving Tesla's autonomous driving advancements.

Development History and Core Specifications

Tesla kicked off its proprietary FSD chip programme in 2016, aiming to eliminate reliance on external suppliers and achieve deep hardware-software synergy through vertical integration. The major milestones across generations are as follows:

Hardware Platform	Process Node	Single/Dual-Chip Compute Performance	Key Features
HW3.0 (First-Generation FSD Chip)	Samsung 14nm	Single chip 72 TOPS, dual chips 144 TOPS	Mass-produced in 2019, integrating a 12-core Cortex-A72 CPU, dual NPUs, and approx. 6 billion transistors
HW4.0 (Second-Generation FSD Chip, AI4)	Samsung 7nm	Approx. 300–500 TOPS	CPU expanded from 12 to 20 cores, NPUs increased to three
HW5.0 (AI5)	TSMC 3nm N3P + Samsung as backup	2,000–2,500 TOPS	Mass production in 2025; dispenses with the GPU and ISP, natively supporting end-to-end AI large models

Technical Highlights

First-Generation FSD Chip (HW3.0)

Fabricated on Samsung's 14nm process, the HW3.0 chip has a die size of approximately 260 square millimetres and packs around 6 billion transistors. Its heterogeneous computing architecture comprises:

CPU: 12 ARM Cortex-A72 cores (3 clusters × 4 cores) clocked at 2.2 GHz
GPU: Mali-G71 MP12 delivering 600 GFLOPS of floating-point processing power
NPU: Dual proprietary neural processing units, each featuring a 96×96 MAC array and 32 MB SRAM, delivering a combined INT8 output of around 73.7 TOPS
ISP: Integrated Image Signal Processor capable of handling 8-channel HDR sensor data with a throughput of up to 1 billion pixels per second

HW3.0 adopts a dual-chip redundant architecture where two FSD chips run concurrently and cross-validate operations, complying with automotive-grade functional safety standards.

AI5 Architecture Shift: A "Less Is More" Philosophy

AI5 (formerly HW5.0) represents a quantum leap in architecture for Tesla's FSD silicon. Elon Musk previously claimed that AI5 delivers 10 times the performance-per-dollar of Nvidia AI chips, alongside three times the efficiency per watt.

Its core engineering approach focuses on simplification:

Removal of GPU and ISP: AI5 completely ditches the dedicated GPU, offloading graphic rendering duties to the infotainment cockpit processor; the ISP has also been eliminated, allowing the NPU to ingest raw 12-bit photon data directly and minimising the loss of raw information caused by image preprocessing
Native Support for End-to-End Large Models: AI5 incorporates customised instruction set optimisations tailored for the FSD V12 pure neural network architecture—for instance, while the SoftMax operation requires a 40-step simulation on AI4, AI5 executes it natively at hardware level in a single step
Half-Reticle Design: Through aggressive streamlining, the AI5 die size is capped within the half-reticle limit, allowing single-exposure photolithography. This significantly boosts production yields and drives down manufacturing costs

On the sensor front, the AI5 hardware suite bumps the camera count from 9 to 12, upgrades camera resolution from 5 MP to 8 MP, and introduces four 4D imaging millimetre-wave radars into the setup.

Industry Outlook

In June 2025, the AI5 chip officially entered mass production, manufactured jointly by TSMC (3nm N3P) and Samsung. Production models equipped with AI5 hardware are slated to commence deliveries in the second half of 2026. Tesla also plans to deploy surplus AI5 chips to its FSD data centres, working alongside Nvidia hardware to support cloud-based AI training workloads.